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We describe the 4th Generation Intel® Core™ processor family (codenamed "Haswell") implemented on Intel® 22 nm technology and intended to support form factors from desktops to fan-less Ultrabooks™. Performance enhancements include a 102 GB/sec L4 eDRAM cache, hardware support for transactional synchronization, and new FMA instructions that double FP operations per clock. Power improvements include Fully-Integrated Voltage Regulators ( 50% battery life extension), new low-power states (95% standby power savings), optimized MCP I/O system (1.0-1.22 pJ/b), and improved DDR I/O circuits (40% active and 100x idle power savings). Other improvements include full-platform optimization via integrated display I/O interfaces.

The desire to deliver breakthrough performance in a tablet form factor required several innovations in the 14nm Intel® flagship Core™ M processor (Broadwell). Better frequency control algorithms including duty cycling graphics cores were developed to improve energy efficiency. New power sharing algorithms were developed to maximize performance of multiple compute domains within tight thermal and power delivery constraints. Innovations resulted in upto 50% increase in performance and upto 25% improvement in battery life over a Haswell system thermally constrained to a 4.5W fanless form factor. Explosive growth in tablets presented an opportunity for the 14nm Intel® flagship Core™ M processor (Broadwell) to target its design specifically for the fanless form factor. Since tablets and laptops are geared for varying performance levels, these devices span a range of form factors. Choice of chassis thickness, materials, components result in a variety of platform power delivery and thermal constraints.Maximizing Performance within Platform Constraints : Power management algorithms on Broadwell factor in power limits (PL*) such as -the long term thermal dissipation limit (PL1), platform power limit (PL2), battery current delivery limit (PL3) and voltage regulator (VR) peak current limit (Iccmax) as depicted in Fig. 1. The power control unit (PCU), implements the control algorithms in firmware using a 32 bit microcontroller. The PCU monitors die temperature, voltage regulator & platform temperature, package power consumption. Various platform limits are provided to the PCU through software knobs. These inputs are fed into proportional integral derivative (PID) control algorithm, to regulate CPU power over a configurable time window. The coefficients for the control law are derived empirically.With mobile devices "skin" or chassis temperature is an important design consideration. As the time constant for chassis thermals is in the order of seconds, the CPU can take advantage of the thermal inertia in the system by boosting CPU performance (Turbo [1]) for short durations, to deliver snappy user response without violating the skin temperature limits [2]. In Fig. 2 platform power management software periodically samples skin temperature sensors and dynamically adjusts PL1 (CPU power consumption) limit, to keep the skin temperature within the acceptable platform limit. Starting from a cold state, the CPU can turbo till the die temperature limit is reached, then CPU power consumption is reduced i.e. PL1 is lowered in order to meet die and skin temperature limits. Later CPU enters low power state, causing a decrease in die and skin temperature. The algorithm detects available thermal headroom and increases the PL1 limit which may allow turbo operation for a short duration. As skin temperature increases beyond 40'C, voltage and frequency of different compute components is reduced to stay within the PL2 limit.Active Power Balancing between CPU sub-systems: With multiple compute resources sharing a common power and thermal envelope...