Recent advances in Boolean satisfiability have made it an attractive engine for solving many digital very-large-scaleintegration design problems. Although useful in many stages of the design cycle, fault diagnosis and logic debugging have not been addressed within a satisfiability-based framework. This work proposes a novel Boolean satisfiability-based method for multiple-fault diagnosis and multiple-design-error diagnosis in combinational and sequential circuits. A number of heuristics are presented that keep the method memory and run-time efficient. An extensive suite of experiments on large circuits corrupted with different types of faults and errors confirm its robustness and practicality. They also suggest that satisfiability captures significant characteristics of the problem of diagnosis and encourage novel research in satisfiability-based diagnosis as a complementary process to design verification.

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We establish the first polynomial time-space lower bounds for satisfiability on general models of computation. We show that for any constant c less than the golden ratio there exists a positive constant d such that no deterministic random-access Turing machine can solve satisfiability in time n c and space n d , where d approaches 1 when c does. On conondeterministic instead of deterministic machines, we prove the same for any constant c less than √ 2. Our lower bounds apply to nondeterministic linear time and almost all natural NP-complete problems known. In fact, they even apply to the class of languages that can be solved on a nondeterministic machine in linear time and space n 1/c . Our proofs follow the paradigm of indirect diagonalization. We also use that paradigm to prove time-space lower bounds for languages higher up in the polynomial-time hierarchy.

Recent advances in Boolean satisfiability have made it an attractive engine for solving many digital VLSI design problems such as verification, model checking, optimization and test generation. Fault diagnosis and logic debugging have not been addressed by existing satisfiability-based solutions. This paper attempts to bridge this gap by proposing a satisfiability-based solution to these problems. The proposed formulation is intuitive and easy to implement. It shows that satisfiability captures significant problem characteristics and it offers different trade-offs. It also provides new opportunities for satisfiability-based diagnosis tools and diagnosis-specific satisfiability algorithms. Theory and experiments validate the claims and demonstrate its potential.

Sensor network which operates on battery are used to gather data in a variety of environments. The data collected by each node is communicated through the network to the sink, which uses all reported data to determine characteristics of the environment or detect an event. Prolonging sensor's operable lifetime is a main design challenge of these networks. A good energy saving technique in this direction is to schedule nodes sleep interval with the communication radio turned off. In this paper, we propose a distributed topology control algorithm, termed ECTC, which uses a clustering approach. It is built on the notion that when a region of a shared channel wireless sensor network has a sufficient density of nodes, significant energy saving is obtained by allowing redundant nodes to sleep. Using the two-hop neighborhood information, certain nodes sequentially select a subset of nodes to be active among all nodes in the neighborhood, to ensure connectivity. Moreover, to ensure fairness, the role of active nodes is rotated periodically to ensure energy-balanced operations. Results from stochastic geometry are used to derive solutions for the values of parameters of our algorithm that minimize the total energy spent in the network when all sensor nodes report data through the cluster heads to the sink.