ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)
DOI: 10.1109/aspdac.2004.1337569
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Design diagnosis using Boolean satisfiability

Abstract: Recent advances in Boolean satisfiability have made it an attractive engine for solving many digital VLSI design problems such as verification, model checking, optimization and test generation. Fault diagnosis and logic debugging have not been addressed by existing satisfiability-based solutions. This paper attempts to bridge this gap by proposing a satisfiability-based solution to these problems. The proposed formulation is intuitive and easy to implement. It shows that satisfiability captures significant pro… Show more

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Cited by 47 publications
(39 citation statements)
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“…These techniques reduce the design debugging problem into a satisfiability problem which can be solved using a formal engine. Over the years, the original SAT-based gate-level debugging formulation [111] has been extended to handle hierarchical RTL blocks [6], and its scalability and performance have improved significantly [6,41,61,63,79,100,110]. However, despite these advances, increasing design sizes and counter-example lengths still present a challenge to automated debugging techniques.…”
Section: Design Debuggingmentioning
confidence: 99%
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“…These techniques reduce the design debugging problem into a satisfiability problem which can be solved using a formal engine. Over the years, the original SAT-based gate-level debugging formulation [111] has been extended to handle hierarchical RTL blocks [6], and its scalability and performance have improved significantly [6,41,61,63,79,100,110]. However, despite these advances, increasing design sizes and counter-example lengths still present a challenge to automated debugging techniques.…”
Section: Design Debuggingmentioning
confidence: 99%
“…In 2004, capitalizing on the major advances in SAT solvers, a SAT-based automated debugging technique was proposed by [111]. It encodes combinational gate-level debugging as a SAT problem, where each satisfying assignment corresponds to a debugging solution.…”
Section: Sat-based Automated Design Debuggingmentioning
confidence: 99%
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“…Logic debugging is a challenging problem as the solution space grows exponentially with the increasing number of errors [12]. This is because the specification is usually treated as a "black box" controllable at the primary inputs and observable at the primary outputs.…”
Section: Introductionmentioning
confidence: 99%
“…To the best of our knowledge, this is the first sequential circuit debugging method based on Boolean Satisfiability. Since logic debugging and fault diagnosis are similar in nature [12], the proposed approach applies to fault diagnosis of chips with no/partial scan chains.…”
Section: Introductionmentioning
confidence: 99%