“…These techniques reduce the design debugging problem into a satisfiability problem which can be solved using a formal engine. Over the years, the original SAT-based gate-level debugging formulation [111] has been extended to handle hierarchical RTL blocks [6], and its scalability and performance have improved significantly [6,41,61,63,79,100,110]. However, despite these advances, increasing design sizes and counter-example lengths still present a challenge to automated debugging techniques.…”