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In medium/high power applications including smart transformers, active power filters and wind turbines, 3-level Neutral-Point-Clamped (NPC) inverters proved to be a reliable solution, providing high efficiency and low harmonic distortion. In practice, several NPCs are parallel connected and operated in interleaved to further increase the power handling and reduce the line filters size. However, if such configuration has a common dc-link, High-frequency Zero-Sequence Circulating Current (HF-ZSCC) arises among the inverters, increasing power losses of the switching devices and propagating the stress on the dc-capacitors. Moreover, the amplitude of the HF-ZSCC is inversely proportional to the filter inductance size, therefore in real applications it can reach hundreds of Amperes even with relatively low output currents. The research on the HF-ZSCC is mostly concentrated on 2-level inverters for low voltage grids and traction applications, where the inductance size is relatively big and the HF-ZSCC does not affect the system efficiency. Differently, NPCs provide higher switching degree of freedom and more sophisticated methods can be applied to reduce the HF-ZSCC. This paper investigates a Double-Reference Pulse-Width Modulation (DRPWM) as solution for diminishing the HF-ZSCC in paralleled NPCs. The performance of DRPWM method is confirmed by both simulation and experiments, performed on a 1.6MVA system. Index Terms-PWM inverters, common dc-link, modulation techniques, circulating current, parallel inverters, neutral-pointclamed inverters I. INTRODUCTION T HREE-LEVEL Neutral-Point-Clamped Voltage-Source Inverters (NPC VSI) have been widely used for decades. Compared to Two-Level VSIs (2L-VSI), the NPC VSI topology offers higher power handling, better current quality and reduced stress on switching devices and capacitors [1]. As a result, the NPC topology is mainly utilized in Medium Voltage (MV) and High Voltage (HV) applications, like smart transformers [2], Static Synchronous Compensators (STATCOM)

This paper proposes a new method to reduce the ripple current of the DC-link capacitor in a two-level voltage source inverter (VSI), with a discontinuous pulse-width modulation (DPWM). In real applications, a capacitor block is very bulky, due to the parallel connection of several capacitors that share the value of the ripple current. Hence, it contributes significantly to the volume and weight of the whole system. Conventional DPWM is used to minimize the amount of switching for the power transistors, therefore, reducing stress and power loss. This leads to increased efficiency and reliability of the system. Nevertheless, the reduction of the DC link ripple current is still not optimal. Therefore, the proposed method introduces a PWM phase-shift technique to provide further reduction of the DC-link ripple current in a DPWM-based VSI. The efficacy of the proposed method is confirmed by simulation and experimental results.

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