To improve the gate oxide long term performance of MOSFETs in back side illuminated CMOS image sensors the wafer back is patterned with suitable through-silicontrenches. We demonstrate that the reliability improvement is due to the annealing of the gate oxide border traps thanks to passivating chemical species carried by trenches.

Field‐effect transistors (FETs), using transition metal dichalcogenides (TMD) as channels, have various types of interfaces, and their characteristics are sensitively changed in temperature and electrical stress. In this article, the effect of fast cyclic thermal stress on the performance of FETs using TMD as a channel is investigated and introduced. The Al2O3 passivation layer is deposited onto the TMD channel by atomic layer deposition process, and the hysteresis decreases and the direction changes from clockwise to counterclockwise. Applying cyclic thermal stress that rapidly heats and cools by 90 K in a 20 s cycle increases and decreases drain current repeatedly as charges move between the TMD channel and the interface traps. As cyclic thermal stress is applied, permanent interfacial damage occurs, resulting in increased interface trap density at the bottom and decreased hysteresis. These experimental results are also shown through technology computer‐aided design simulations. In addition, series resistance and mobility attenuation factor increase due to the concentration of the conduction paths at the bottom of the channel.

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