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Power consumption has become a major design constraint in the embedded systems domain and techniques such as dynamic voltage and frequency scaling (DVFS) have emerged to enhance the system's power and energy efficiency. DVFSenabling voltage regulators influence the performance, power and energy efficiency of such systems, however, this impact is often neglected or considered late in the design process. In this work, we propose DVFS hardware extensions to a power emulation approach for modeling the voltage regulator behavior, which allows for performance, power and energy efficiency investigations of DVFS-enabled embedded systems. The power emulation approach delivers real-time power information in an early design phase, which allows for the exploration of DVFS efficiency before silicon is available. This offers greater freedom to designers to determine the most apt voltage regulator yielding a system that meets performance, power and energy constraints.

In recent years the wide spread introduction of small embedded systems into every corner of everyday life lead to the strong need for highly reliable and secure computing machines. These machines now affect the safety of humans as well as the security of personal data and consequently money transactions. To ensure the integrity of these systems' operating state, several fault detection mechanisms have been developed to safely correct or stop unforeseen execution behavior. Because of the rise of battery or even field-supplied systems these mechanisms often heavily decrease available power budgets or lead to significantly increased production costs.Therefore, this paper introduces novel micro-architectural execution signature characterization and handling techniques for system-on-chip designs providing power estimation hardware. Existing power sensor infrastructure is reused to enable efficient system-state monitoring using micro-architectural hashes to cover a wide range of implemented system functionality. Reduced hashing implementations are characterized for their fault detection efficiency. This hardware-based approach provides a completely transparent solution to counteract faults resulting from emerging wear-out defects or intentional attacks on the execution integrity.

Power-aware hardware/software codesign defines a design methodology for the development of energy efficient embedded systems. With the appearance of energy-harvesting devices or RF-powered smart cards in recent years, the focus of the design process has been shifting from purely energy-oriented to power-constraints-oriented optimization strategies.In this paper we present an overview of various codesign flows and we motivate the importance of power awareness in today's design processes. Moreover, the industrial relevance of hardware/software codesign is shown in a case study of an RF-powered smart card system. Keywords: power awareness; hardware/software codesign; smart cards; power emulation Power-aware Hardware/Software Codesign fü r mobile Systeme.Power-aware Hardware/Software Codesign definiert eine Design-Methode fü r die Entwicklung energieeffizienter, eingebetteter Systeme. Durch das verstä rkte Aufkommen von Gerä ten, die ihre Energie aus der Umgebung beziehen ("Energy Harvesting") oder kontaktlos ü ber ein RF-Feld versorgt werden, hat sich auch der Fokus des Designprozesses verlagert. Statt sich ausschließlich auf die Energieoptimierung zu konzentrieren, mü ssen nun auch immer stä rker Einschrä nkungen bezü glich der Leistungsaufnahme berü cksichtigt werden.In diesem Artikel werden verschiedene Codesign-Flows vorgestellt und deren Bedeutung in der Entwicklung von leistungs-und energieeffizienten Systemen unterstrichen. Darü ber hinaus wird die industrielle Relevanz des Hardware/Software Codesigns anhand eines konkreten Anwendungsfalls in der Anwendungsdomä ne von kontaktlosen Chipkarten gezeigt.