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In this article we present a full physical analytical model (FAM) for symmetric double-gate amorphous oxide semiconductor TFTs (DG AOSTFTs). The current-voltage (I-V) model is physically described for the above-threshold operation regime. In this case, the general expression for the field effect mobility is evaluated for the potential at the centre of the semiconductor layer at V G = 1 + V T , obtaining the value of the mobility parameter called µ 1DG for DG-AOSTFT. This parameter can now be used to represent the field effect mobility expression like in the model known as the unified model and extraction method, which is widely used for modelling amorphous devices. The proposed FAM model contains the analytical capacitances-voltage (C-V) model and considers the specific characteristics of DG structures, including the potential different from zero, at the centre of the semiconductor layer. The model was described in Verilog-A for introducing in Silvaco's SmartSpice simulation program and was validated with simulated data and experimental characteristics of reported DG amorphous indium-galium-zinc oxide devices.

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This article presents formulations for the voltage-in-current (VinC) latency insertion method (LIM) for thin-film transistors (TFTs). LIM is a fast circuit simulation algorithm that solves circuits in a leapfrog manner, without requiring intensive matrix operations present in SPICE-based simulators. This allows LIM to have a far superior scaling with respect to the size of the circuit resulting in significant time savings on large circuit networks. The VinC LIM formulation for the TFTs written in this article has the benefit of a better stability compared to the original LIM formulation which allows the use of larger time steps. The performance of the new algorithm is demonstrated through the simulation of numerical examples of large flat-panel display (FPD) circuits. It is seen that VinC LIM greatly outperforms basic LIM and commercial SPICE-based simulators, where the presented algorithm is able to simulate circuits with more than 10 million nodes or devices in a reasonable time, which is not viable in many modern day SPICE-based simulators.INDEX TERMS Circuit analysis, latency insertion method, thin-film transistor