The evolution of porous silicon (PSi) from its early studies in the late 70’s toward its industrial application in microelectronics is described in this article. The way this material can be integrated now in many devices at a wafer level is shown in this paper through examples of prototypes that include PSi in their fabrication process. For instance, realization of devices on large area wafers in the field of RF passive components, energy micro-sources or porous flexible membranes are described. In this paper, we also show recent advances in the field of PSi etching and integration at an industrial level. In particular, we put an emphasis on reproducibility and homogeneity issues, on the wafer warp management using different annealing procedures.

The resistivity of p type porous silicon (PS) is reported on a wide range of PS physical properties. Al/PS/Si/Al structures were used and a rigorous experimental protocol was followed. The PS porosity (P%) was found to be the major contributor to the PS resistivity (ρPS). ρPS increases exponentially with P%. Values of ρPS as high as 1 × 109 Ω cm at room temperature were obtained once P% exceeds 60%. ρPS was found to be thermally activated, in particular, when the temperature increases from 30 to 200 °C, a decrease of three decades is observed on ρPS. Based on these results, it was also possible to deduce the carrier transport mechanisms in PS. For P% lower than 45%, the conduction occurs through band tails and deep levels in the tissue surrounding the crystallites. When P% overpasses 45%, electrons at energy levels close to the Fermi level allow a hopping conduction from crystallite to crystallite to appear. This study confirms the potential of PS as an insulating material for applications such as power electronic devices.

In this study, we show I-V characterizations of various metal/porous silicon carbide (pSiC)/silicon carbide (SiC) structures. SiC wafers were electrochemically etched from the Si and C faces in the dark or under UV lighting leading to different pSiC morphologies. In the case of low porosity pSiC etched in the dark, the I-V characteristics were found to be almost linear and the extracted resistivities of pSiC were around 1.5 × 104 Ω cm at 30 °C for the Si face. This is around 6 orders of magnitude higher than the resistivity of doped SiC wafers. In the range of 20-200 °C, the activation energy was around 50 meV. pSiC obtained from the C face was less porous and the measured average resistivity was 10 Ω cm. In the case high porosity pSiC etched under UV illumination, the resistivity was found to be much higher, around 1014 Ω cm at room temperature. In this case, the extracted activation energy was estimated to be 290 meV.