With the development in the field of quantum physics, several methods for building a quantum computer have emerged. These differ in qubit technologies, interaction topologies, and noise characteristics. In this article, insights are given into the circuitcentric architecture design of Noisy Intermediate-Scale Quantum (NISQ) devices. The dependence of the circuit size, circuit depth on the interaction and connection between different qubits present in quantum hardware are discussed. A noise-aware procedure is presented which helps in determining the optimal interactions between different qubits of a quantum chip to execute a given circuit in the most efficient way possible. In this article, the 5-qubit hardware in a noiseless setting is illustrated with an example. Also, a benchmark-driven analysis is performed to show the importance of noise adaptivity in determining the hardware reliability. It is concluded that a generalized and flexible procedure such as this approach can aid in determining the design of hardware accurately for which the circuit runs efficiently, that is, with the least number of clock cycles, the lowest gate operations, and noise-based errors. This is an open access article under the terms of the Creative Commons Attribution-NonCommercial-NoDerivs License, which permits use and distribution in any medium, provided the original work is properly cited, the use is non-commercial and no modifications or adaptations are made.