The triple-dielectric polysilicon-blocking oxidesilicon nitride-tunnel oxide-silicon (SONOS) structure is an attractive candidate for high density E 2 PROM's suitable for semiconductor disks and as a replacement for high-density dynamic random access memories (DRAM's). Low programming voltages (5 V) and high endurance (greater than 10 7 cycles) are possible in this multidielectric technology as the intermediate Si 3 N 4 layer is scaled to thicknesses of 50Å. The thin gate insulator and low programming voltage enable the scaling of the basic memory cell and associated complementary metal-oxide-semiconductor (CMOS) peripheral circuitry on the memory chip. A SONOS 1TC memory cell is proposed in a NOR architecture with a cell area of 6F 2 , where F is the technology feature size. A 0.20 m feature size permits a 1TC area of 0.24 m 2 for advanced 1-Gb nonvolatile semiconductor memory chips. A physical model is presented to characterize the erase/write, retention and endurance properties of the nonvolatile semiconductor memory (NVSM) SONOS device.

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