A low voltage SONOS nonvolatile semiconductor memory technology

Abstract

The triple-dielectric polysilicon-blocking oxidesilicon nitride-tunnel oxide-silicon (SONOS) structure is an attractive candidate for high density E 2 PROM's suitable for semiconductor disks and as a replacement for high-density dynamic random access memories (DRAM's). Low programming voltages (5 V) and high endurance (greater than 10 7 cycles) are possible in this multidielectric technology as the intermediate Si 3 N 4 layer is scaled to thicknesses of 50Å. The thin gate insulator and low programming voltage enable the scaling of the basic memory cell and associated complementary metal-oxide-semiconductor (CMOS) peripheral circuitry on the memory chip. A SONOS 1TC memory cell is proposed in a NOR architecture with a cell area of 6F 2 , where F is the technology feature size. A 0.20 m feature size permits a 1TC area of 0.24 m 2 for advanced 1-Gb nonvolatile semiconductor memory chips. A physical model is presented to characterize the erase/write, retention and endurance properties of the nonvolatile semiconductor memory (NVSM) SONOS device.

Charge stability in LPCVD silicon nitride for surface passivation of silicon solar cells

“…The saturated negative charge density is ~4.74x10 12 cm -2 in this case. Studies on NVMs [5] have shown that several mechanisms are responsible for charge decay in the nitride. However, the dominant mechanism, particularly at elevated temperatures, consists of the thermal emission of carriers from the negatively charged (K -) centre to the nitride conduction band, followed by Fowler-Nordheim tunnelling across the tunnel oxide.…”

“…The manipulation of the SiNx charge state by charge injection has been exploited for non-volatile memory devices (NVMs). [5,6] In this paper, we investigate the stability of silicon dioxide/silicon nitride stacks in more detail, in order to determine under what conditions the charge is sufficiently stable for photovoltaic applications.…”

Self-assembly of metal nanocrystals on ultrathin oxide for nonvolatile memory applications

“…[1][2][3] For semiconductor nanocrystal memories, the role of traps and defects inside or at the surface of nanocrystals can explain the experimental observation of long-term retention, 4 which makes their operational principle similar to trap-based storage. 5 The control of trap levels and density is thus critical for consistency in long retention time. This is, however, difficult because of the high sensitivity of trap formation and annihilation during the annealing process.…”

Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals

“…Tunneling oxide thickness below 7 nm must confront a number of challenges, including large stress-induced leakage current (SILC), serious short-channel effect, and critical floating-gate coupling effect [2]- [4]. The most serious issue among these challenges is the increase of the tunneling oxide leakage current induced by program/erase cycling stress, resulting in data retention degradation when the tunneling oxide is scaled below 7 nm [3].…”