This paper presents a power-and area-efficient multistandard serial link transceiver designed for backplane application rates of up to 28 Gb/s, such as OIF CEI-25G, CEI-28G, and IEEE 802.3bj 100G-KR4. The receiver features a continuous-time linear equalizer, variable gain amplifier, and a 14-tap decision feedback equalizer, including eight floating taps. The transmitter has a 2:1 multiplexer with a duty cycle distortion corrected half-rate clock and a full-rate source-series terminated driver with a 5-tap feed-forward equalizer. The shared PLL employs a transformer-based LC-VCO that achieves a VCO tuning range of 20G to 29 GHz and 0.23 ps RMS jitter at 28.125 GHz. The transmitter output shows only 50 fs duty-cycle distortion. The transceiver can compensate a 40 dB insertion loss backplane channel (excluding package) at a data rate of 25.78 Gb/s with eight channels running simultaneously. It is fabricated in 28 nm standard CMOS and analog section consumes only 295 mW at 1 V supply with transmitter driver at 1.25 V. Such low power consumption and performance are achieved by combination of advanced 28 nm process, low power and performance driven receiver and transmitter topologies, widely adopted bandwidth extension techniques, built-in analog calibrations and one common PLL with a transformer based VCO for four transceivers.Index Terms-Backplane, continuous-time linear equalizer, decision feedback equalizer, duty-cycle distortion, feed-forward equalizer, 40 dB insertion loss, quarter-rate topology, serial link transceiver, source-series terminated driver, tap timing, 25G.

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Broadcom, Irvine, CA Rapid internet traffic growth has fueled the demand for bandwidth in metro networks and data centers and pushed the serial link data rate into 25Gb/s territory, populated by such electrical interface as OIF CEI-25G, CEI-28G [1], IEEE 802.3bj 100G-KR4. To cope with severe channel impairments at 25Gb/s with up to 30dB loss at Nyquist, a feed-forward equalizer (FFE)/decision feedback equalizer (DFE) based transceiver without power-hungry analog-todigital converter (ADC) provides robust performance. This work presents a low-power and area-efficient transceiver that employs a 14-tap adaptive DFE at the receiver (RX) and a 5-tap FFE at the transmitter (TX) for multi-standard applications up to 28Gb/s in 28nm CMOS.

It has been well understood that the digital clock and data recovery (CDR) architecture has many system merits over the analog counterpart for multi-Gb/s transceivers [1]. However, the applications have been limited in systems where the clock is forwarded or has small frequency offset [2,3], due to the finite frequency and jitter tracking capability of the digitally controlled phase rotation. Recently, tracking range up to ±7800ppm has been reported [4] to extend the applications to the SATA/SAS interfaces that require 5000ppm spread spectrum clocking (SSC) to suppress electromagnetic emissions. To enable broad acceptance in high-speed applications, the digital CDRs must have much wider tracking range.First, it is highly desirable to use an on-chip (CMOS) clock available at any frequency F ref as the reference for the fixed frequency PLL. This requires the CDR to track any fractional frequency offset within ±F ref assuming the integer feedback divider ratio N programmable at a step size of 2. The ratio ±F ref / F baud amounts to ±5kppm, given F ref in the low tens MHz range (e.g., 27MHz) and the data rate F baud in the multi-Gb/s range (e.g., 6Gb/s). Second, the CDR needs to be wideband to track out the low frequency jitter from the clock reference, the VCO, the power supply and other noise sources in the system. The jitter can be tens of unit intervals (UIs) as is specified by many sinusoidal jitter (SJ) tolerance masks that roll-off at 20dB/dec and settle to SJ min ~ 0.5UI at frequencies F SJ > F baud /1000. The SJ translates to a maximum frequency variation of ±(2πF baud /1000) × SJ min~ ±3000ppm. Finally, there is an increasing demand for ±5kppm and more SSC. The overall frequency tracking range spec is therefore ±5kppm (offset) ±3kppm (SJ) ±5kppm (SSC) = ±13kppm. This paper presents an 8Gb/s digital CDR that achieves a tracking range of ±15.6kppm and a tracking bandwidth up to 10MHz. Figure 25.4.1 shows the block diagram of a 1.25 to 8Gb/s SerDes transceiver in 40nm CMOS that incorporates the digital wideband CDR. Along with the adaptive peaking equalization, TX pre-emphasis, and SSC generation in the transceiver, the digital CDR supports applications such as SATA/SAS, USB3.0, PCIe, DisplayPort, EPON, etc. Special features such as the host tracking for HDD SATA and the loop timing for passive optical network (PON) applications are realized by looping the digital phase rotation signal from the CDR to the TX side phase interpolator (PI) through a programmable IIR filter without the need for a costly analog clean-up filter.The CDR performance is achieved through architecture optimization and circuit innovations. The first two architecture decisions are on the demux ratio and the resolution of phase rotation, which together determine the tracking range. Demultiplexing by 1-to-4 maximizes the speed without causing substantial latency overhead from pipelining the digital operations; a resolution of 32 phase steps is chosen as a result of trade-off between the quantization noise and the rotation speed. As is shown ...