A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS

Abstract

This paper presents a power-and area-efficient multistandard serial link transceiver designed for backplane application rates of up to 28 Gb/s, such as OIF CEI-25G, CEI-28G, and IEEE 802.3bj 100G-KR4. The receiver features a continuous-time linear equalizer, variable gain amplifier, and a 14-tap decision feedback equalizer, including eight floating taps. The transmitter has a 2:1 multiplexer with a duty cycle distortion corrected half-rate clock and a full-rate source-series terminated driver with a 5-tap feed-forward equalizer. The shared PLL employs a transformer-based LC-VCO that achieves a VCO tuning range of 20G to 29 GHz and 0.23 ps RMS jitter at 28.125 GHz. The transmitter output shows only 50 fs duty-cycle distortion. The transceiver can compensate a 40 dB insertion loss backplane channel (excluding package) at a data rate of 25.78 Gb/s with eight channels running simultaneously. It is fabricated in 28 nm standard CMOS and analog section consumes only 295 mW at 1 V supply with transmitter driver at 1.25 V. Such low power consumption and performance are achieved by combination of advanced 28 nm process, low power and performance driven receiver and transmitter topologies, widely adopted bandwidth extension techniques, built-in analog calibrations and one common PLL with a transformer based VCO for four transceivers.Index Terms-Backplane, continuous-time linear equalizer, decision feedback equalizer, duty-cycle distortion, feed-forward equalizer, 40 dB insertion loss, quarter-rate topology, serial link transceiver, source-series terminated driver, tap timing, 25G.

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection

“…The proliferation of copper-based links in this area can be mainly attributed to the advancements of CMOS technologies and circuit techniques. By utilizing advanced CMOS technologies and equalization techniques, operations at higher than 25 Gb/s even in severe loss conditions of more than 40 dB were achieved [ 9 , 10 , 11 ]. Recently, circuit designers attempt to overcome the limitations of copper by introducing a pulse-amplitude-modulation (PAM) signaling that can enhance the effective data rate for the same loss condition as the conventional binary signaling [ 12 , 13 , 14 , 15 ].…”

A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology

“…According to (4) and (5), the implementation of the PD and SS-LMS logic are exhibited in Fig. 23(a) and (b) separately.…”

“…1 shows a traditional half-rate TX architecture including a data path and a clock path. In the data path, the source-series terminated (SST) driver topology is considered as an attractive solution for low power consumption [4]- [6]. However, few measures are taken to save the power of the clock path even though it is usually as high as that of the data path.…”

“…The feed-forward equalizer (FFE) is normally employed as the TX equalization. However, for the multichannel applications, the crosstalk between the multi-parallel channels also exacerbates the signal integrity [4], which cannot be resolved by the FFE. To mitigate the far-end crosstalk (FEXT) and the crosstalk-induced jitter (CIJ), several approaches using a crosstalk canceller (XTC) have been adopted in the designs of TX [11], [12].…”

“…1) is considered to be a good compromise between performance, complexity, and power [4]. Due to the strong equalization ability without enhancement of the noise and crosstalk, the decision-feedback equalizer (DFE) has become the most attractive approach at the RX side.…”