No abstract

A non-closed-form general mathematical model for CMOS distributed amplifier (DA) for broadband applications is presented. Contrary to the artificial transmission line (TL) assumption made in the conventional analytical models, the proposed model treats the DA as a discrete set of cells connected together, and hence considers propagation and mismatch between inter-cells. This approach provides designers with a much more accurate first sizing of the DA compared to conventional ways and, as a result, leads to a reduced design time and complexity. The model enables both quantitative and qualitative analysis of a DA, for the purpose of aiding the designers in predicting the relations between DA performance and its multi-design parameters, especially in the context of nonuniform designs. In addition, it is well suited to Computer-Automated Design (CAutoD), to help in achieving designs having a given set of performance goals. The validation of the model is demonstrated on two designs, by a comparison with simulations done in Keysight's ADS tool and using STMicroelectronics' 55-nm SiGe BiCMOS design kit. First design is inspired from an already published non-uniform DA design while second one proposes a 100-GHz bandwidth CMOS uniform DA with 8 dB of power gain, after using it in a CAutoD process.

A wideband fully-integrated bias-tee well suited for millimeter waves is presented. Compared to conventional bias-tees, where RF-choke is optimized on the basis of its inductance value, here, the proposed RF-choke takes advantage of its low parasitic capacitance as one of the design parameters. While enabling wideband operation, in particular towards lower frequencies, this bias-tee enables ease-ofimplementation, robustness against resonance, efficient power delivery to the intended wideband circuit and contributes to circuit area reduction on integrated circuit (IC) implementation. As a proof-of-concept, a wideband CMOS distributed amplifier (DA) with a lower-corner frequency (𝑭 𝒍𝒐𝒘𝒆𝒓 ) of 5 GHz and an upper-corner frequency (𝑭 𝒖𝒑𝒑𝒆𝒓 ) close to 100 GHz is implemented in STMicroelectronics' 55-nm technology with the proposed bias-tee connected to its artificial drain line. The implemented bias-tee enabled a bandwidth close to 100 GHz and its RF-choke required a surface area of 82 µm x 82 µm. When integrated along with the DA, the overall chip area remained the same (0.89 mm 2 ). Post-layout simulations showed a DC power overhead (due to inclusion of the on-chip bias-tee) limited to 17% of the DA-only consumption.

This paper aims to compare the performance of HBT-based and MOSFET-based mm-Wave SPDT switches in a single BiCMOS technology. To the best of authors' knowledge, a direct comparison of this function in the same integrated process has never been reported before. Measurement results on two 50-GHz integrated SPDTs reveal that the HBT-based SPDT switch yields 1.7 dB of insertion loss and 14 dB of isolation in its central frequency, with a bandwidth covering the 30-80 GHz frequency range when considering a return loss greater than 10 dB. On the other hand, the MOSFET-based SPDT switch yields 2.1 dB of insertion loss and 12 dB of isolation at center frequency and a bandwidth covering the 33-80 GHz frequency range.