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This paper presents a novel signal frequency multiplier for very high speed applications. The proposed circuit is based on a simple but effective folding cell and it is able to generate an output at four times the frequency of the differential sine wave input. The circuit has been designed and optimized for a 40-nm CMOS technology and it has been fully simulated at the transistor level. Possible fabrication and timing mismatches are corrected with foreground calibration. Simulation results shows that the multiplier can provide an output signal at 40 GHz starting from a 10-GHz input signal consuming about 5 mW.

In this paper we present a complete low-voltage, lowpower and high linearity CMOS interface circuit for fluxgate magnetic sensors for current measurement applications. The integrated circuit provides the correct excitation signal to the fluxgate sensors and reads-out the sensor signals from the sensing coils. The proposed circuit allows us to deal with sensors featuring different values of the excitation coil resistance and to process the sensing coil signals with a power consuption lower than 1 mW. The interface circuit consists of three different modules, namely a timing block, an excitation block and a read-out chain. The interface circuit, has been implemented with two different excitation circuits, operating at 5 V and 3.3 V, respectively, without any high-voltage process options. The read-out chain performs a synchronous demodulation of the even harmonics, in order to extract the value of the external magnetic field. Furthermore, it is possible to switch-on a 13 bit ADC, to provide at the output the demodulated signal as a digital word.

A 12.5 GS/s 5-bit A/D converter is described. The architecture is a hybrid scheme with flash, single and double folding, able to obtain the optimum trade off between speed and power consumption. Simulations at the transistor level validate the proposed architecture.