Time variant digital sigma-delta modulator for fractional-N frequency synthesizers

Maloberti, Franco; Bonizzoni, Edoardo; Surano, Antonio

doi:10.1109/rfit.2009.5383735

Cited by 5 publications

(7 citation statements)

References 5 publications

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“…The origin of fractional spurs is attributed to the limited sequence length of modulator's output; thus more power converges onto some certain spectral tones. Solutions are classified into two types -deterministic [3][4] and stochastic [1] [2]. Deterministic approaches modify the DDSM's structure or set up an irrational condition to disrupt the modulator's internal states.…”

Section: Previous Solutionsmentioning

confidence: 99%

“…An unwanted task to implement the dithering is that the PN generator has to be specifically designed with extra circuits. It is commonly realized with linear-feedback-shiftregisters (LFSR) [4], while a recently published method employs another accumulator together with an 11-stage LFSR to dither the DDSM's coefficients [2]. Indeed, such extra endeavor can be avoided by applying the method proposed in the following section.…”

Section: Previous Solutionsmentioning

confidence: 99%

“…The MASH posses advantages of stability and considerable noise shaping, while single-loop modulators are conditionally stable but enable a flexibly optimized noise transfer function (NTF). Unfortunately, both of them suffer from spurious tones which finally appear at the PLL's output spectrum, known as "fractional spurs", degrading the fractional-N PLL's spectral purity [2]. To solve this problem, several solutions have been proposed which will be discussed in the following sections.…”

Section: Introductionmentioning

confidence: 99%

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Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL

Lee

Masui

2011

IEICE Trans. Electron.

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Section: Previous Solutionsmentioning

confidence: 99%

Section: Previous Solutionsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL

Lee

Masui

2011

IEICE Trans. Electron.

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“…Many methods have been proposed to improve the statistical properties of the e 0 sequence for a generic input. We consider here the method first proposed in [9] which consists on varying the accumulator's feedback coefficients with time, as shown in Fig. 2.…”

Section: Introductionmentioning

confidence: 99%

A Pseudorandom Number Generator Based on Time-Variant Recursion of Accumulators

González-Díaz

Pareschi

Setti

et al. 2011

IEEE Trans. Circuits Syst. II

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This paper presents a PseudoRandom Number Generator (PRNG) that requires very low resources from the hardware design point of view. It is based on a chain of digital accumulators whose coefficients are varied by an auxiliary, low complexity, Linear Feedback Shift Register (LFSR). We present a predictability and periodicity analysis of the sequences generated by the proposed architecture to show that the system is a good candidate to be used for applications requiring high-quality pseudorandom sequences in portable devices. The statistical behavior of the proposed solution is also validated by tests from the National Institute of Standards and Technology (NIST). The generated pseudorandom sequences pass all tests both at levelone and level-two approaches.

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“…Digital Sigma-Delta Modulator [44] made from accumulator circuits. This latter is used to divide the frequency in a Fractional-n Frequency Synthesizer [45].…”

mentioning

confidence: 99%

Survey on hardware implementation of random number generators on FPGA: Theory and experimental analyses

Bakiri

Guyeux

Couchot

et al. 2018

Computer Science Review

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Random number generation refers to many applications such as simulation, numerical analysis, cryptography etc. Field Programmable Gate Array (FPGA) are reconfigurable hardware systems, which allow rapid prototyping. This research work is the first comprehensive survey on how random number generators are implemented on Field Programmable Gate Arrays (FPGAs). A rich and upto-date list of generators specifically mapped to FPGA are presented with deep technical details on their definitions and implementations. A classification of these generators is presented, which encompasses linear and nonlinear (chaotic) pseudo and truly random number generators. A statistical comparison through standard batteries of tests, as well as implementation comparison based on speed and area performances, are finally presented.

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Time variant digital sigma-delta modulator for fractional-N frequency synthesizers

Cited by 5 publications

References 5 publications

Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL

Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL

A Pseudorandom Number Generator Based on Time-Variant Recursion of Accumulators

Survey on hardware implementation of random number generators on FPGA: Theory and experimental analyses

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