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Abstract:In this letter, a new all digital phase locked loop (ADPLL) is proposed. The proposed ADPLL is introduced a new locking procedure with low complexity which results in an ultra low power design. The design uses only two up-down counters for finding the reference frequency. An efficient glitch removal filter and a new low power DCO are also introduced in this letter. The DCO achieves a reasonably high resolution of 1 ps. The power consumption of the proposed ADPLL at 500 MHz frequency is 820 µW. The proposed ADPLL is simulated in 180 nm CMOS with Hspice and verified by MATLAB.

Abstract:In this paper, an ultra low power 15-bit digitally controlled oscillator (DCO) is proposed. The proposed DCO is designed based on a segmental coarse-tuning stage which employs novel Schmitttrigger based hysteresis delay cells (HDC) as well as digitally controlled varactor (DCV) in the fine-tuning stage. Simulation of the proposed DCO using TSMC 180 nm model achieves controllable frequency range of 191 MHz ∼ 850 MHz with a wide linearity. Monte Carlo simulation demonstrates that the time-period jitter due to random power supply fluctuation is under 124.8 ps and the power consumption is 137 µW at 215 MHz with 1.8 V power supply.

In the present article, a low-power dual band all digital PLL is proposed. Our recently developed dual band oscillator used in the structure of this dual band ADPLL. In the proposed ADPLL, toggling the input control bit utilizes the ADPLL to switch between two different frequency bands. Sustaining coarse and fine characteristics and with a combination of capacitive shift and Schmitt trigger techniques, this oscillator changes the trigger points of the circuit and thus results in variable delay and therefore, in creation of two different frequency bands. This can be used in situation when there is a need to switch between two different frequencies for two different application or multi-standard bands. In such an occasion, instead of using two ADPLLs, the proposed structure, which reduces the needed area, utilized. Moreover, in this method, there is no need for redesigning and evaluating the degree of stability against voltage changes, temperature and process of two ADPLLs. Simulation of the proposed dual band ADPLL is performed with HSPICE by a voltage VDD=1.8v in 180nm and CMOS technology. The frequency of the proposed oscillator ranges from 97.18MHz to 117.65MHz in lower band and 134.05MHz to 177.03MHz in the upper band.Keywords-Dual-band all digital phase locked loop, Dual-band digitally controlled oscillator, Phase and frequency detector, jitter, low power

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