International audienceWell known as an efficient and eco-friendly power source, fuel cell, unfortunately, offers slow dynamics. When attached as primary energy source in a vehicle, fuel cell would not be able to respond to abrupt load variations. Supplementing battery and/or supercapacitor to the system will provide a solution to this shortcoming. On the other hand, a current regulation that is vital for lengthening time span of the energy storage system is needed. This can be accomplished by keeping fuel cell's and batteries' current slope in reference to certain values, as well as attaining a stable dc output voltage. For that purpose, a feedback control system for regulating the hybrid of fuel cell, batteries, and supercapacitor was constructed for this study. Output voltage of the studied hybrid power sources (HPS) was administered by assembling three dc-dc converters comprising two bidirectional converters and one boost converter. Current/voltage output of fuel cell was regulated by boost converter, whereas the bidirectional converters regulated battery and supercapacitor. Reference current for each converter was produced using Model Predictive Control (MPC) and subsequently tracked using hysteresis control. These functions were done on a controller board of a dSPACE DS1104. Subsequently, on a test bench made up from 6 V, 4.5 Ah battery and 7.5 V, 120 F supercapacitor together with a fuel cell of 50 W, 10 A, experiment was conducted. Results show that constructing a control system to restrict fuel cell's and batteries' current slope and maintaining dc bus voltage in accordance with the reference values using MPC was feasible and effectively done

In data communication via internet, security is becoming one of the most influential aspects. One way to support it is by classifying and filtering ethernet packets within network devices. Packet classification is a fundamental task for network devices such as routers, firewalls, and intrusion detection systems. In this paper we present architecture of fast and reconfigurable Packet Classification Engine (PCE). This engine is used in FPGA-based firewall. Our PCE inspects multi-dimensional field of packet header sequentially based on tree-based algorithm. This algorithm simplifies overall system to a lower scale and leads to a more secure system. The PCE works with an adaptation of single cycle processor architecture in the system. Ethernet packet is examined with PCE based on Source IP Address, Destination IP Address, Source Port, Destination Port, and Protocol fields of the packet header. These are basic fields to know whether it is a dangerous or normal packet before inspecting the content. Using implementation of tree-based algorithm in the architecture, firewall rules are rebuilt into 24bit sub-rules which are read as processor instruction in the inspection process. The inspection process is comparing one subrule with input field of header every clock cycle. The proposed PCE shows 91 MHz clock frequency in Cyclone II EP2C70F896C6 with 13 clocks throughput average from input to output generation. The use of tree-based algorithm simplifies the multidimensional packet inspection and gives us reconfigurable as well as scalable system. The architecture is fast, reliable, and adaptable and also can maximize the advantages of the algorithm very well. Although the PCE has high frequency and little amount of clock, filtering speed of a firewall also depends on the other components, such as packet FIFO buffer. Fast and reliable FIFO buffer is needed to support the PCE. This PCE also is not completed with rule update mechanism yet. This proposed PCE is tested as a component of FPGA-based firewall to filter Ethernet packet with FPGA DE2 Board using NIOS II platform.

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