In this work, the electrical properties of dislocation loops and their role in the generation of leakage currents in p-n or Schottky junctions were investigated both experimentally and through simulations. Deep Level Transient Spectroscopy (DLTS) reveals that the implantation of silicon with 2 × 1015 Ge cm−2 and annealing between 1000 °C and 1100 °C introduced two broad electron levels EC − 0.38 eV and EC − 0.29 eV in n-type samples and a single broad hole trap EV + 0.25 eV in the p-type samples. These trap levels are related to the extended defects (dislocation loops) formed during annealing. Dislocation loops are responsible for the significant increase of leakage currents which are attributed to the same energy levels. The comparison between structural defect parameters and electrical defect concentrations indicates that atoms located on the loop perimeter are the likely sources of the measured DLTS signals. The combined use of defect models and recently developed DLTS simulation allows reducing the number of assumptions and fitting parameters needed for the simulation of leakage currents, therefore improving their predictability. It is found that simulations based on the coupled-defect-levels model reproduce well the measured leakage current values and their field dependence behaviour, indicating that leakage currents can be successfully simulated on the exclusive basis of the experimentally observed energy levels.

The fabrication technology of extra‐functionality CMOS devices involves process steps which lead to high damage in the silicon lattice. Amorphizing implants and simultaneous reduction of thermal budgets to gain better control of the formation of ultra‐shallow junctions render the presence of extended defects in active regions unavoidable. In particular, dislocation loops (DLs) have proven to be stable under thermal treatment. To better understand the electrical properties of DLs and their impact on the leakage current we developed an analytical tool to extract defect parameters from measured Deep Level Transient Spectroscopy (DLTS) signals and capacitance transients. Commercial process and device simulators are used to test the plausibility of applied defect models and the basic assumptions about the electrical activity of DLs. Simulation of DLTS peak broadening caused by the broadening of a defect level distribution in the band gap of silicon.

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