No abstract

In this study, the potential of HfSiON as the node dielectric of deep-trench (DT) capacitors was investigated for the first time. It was found out that a uniform thickness and a uniform depth profile of each component in DT can be obtained by the ALD process which utilizes the catalytic effect of the Hf precursor and Si precursor. In addition, the mechanism underlying leakage current was analyzed and it was revealed that residual carbons in the film contribute to the Poole–Frenkel current through the film. On the basis of these findings, we propose the sequential high-pressure ozone treatment (SHO) and Al2O3/HfSiON/Si3N4 stack for DT applications. Finally, the DT capacitors of 65-nm-node embedded dynamic random-access memory (eDRAM) were fabricated and a capacitance enhancement of 50% from the conventional dielectric (NO) was obtained at the same leakage current.

The microminiaturization of semiconductor devices has made it necessary to control the wet etching process on the nanometer order. It is therefore extremely important to understand wet etching reactions in the nanoscale region of solid-liquid interfaces, in order to assist in optimizing process conditions to satisfy the severe demand for semiconductor devices. Simulations performed to analyze the behavior of liquid molecules in the nanoscale region have been reported [1], but there have been few reports of detailed experimental results. We here report detailed experimental results on the wet etching behavior of SiO2 film in the nanoscale region between Si materials.

ALD HfSiOx was applied to the node dielectric of deep trench (DT) capacitors of the 65nm node embedded DRAM (eDRAM) for the first time. As a result, capacitance enhancement of 30% from the conventional dielectric (NO) was achieved at the same level of leakage current. The main features of our ALD process are 1) a uniform thickness and depth profile of each component in DT by taking advantage of a catalytic effect of the precursors and 2) a reduced amount of impurities in the film without causing any degradation of step coverage.

We investigated the effect of Si wet etching on the vertical step at wafer edge. We found that the concave-convex shape appeared at the wafer edge after Si etching by the Atomic Force Microscopy analysis. From the liquid simulation and the detailed evaluation of Si etching rate, we revealed that the concave-convex shape was formed by the distribution of the fluid velocity at the wafer edge.