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A programmable sequencer and a memory module have been designed and built to demonstrate high speed operation of the FASTBUS, and to study design implications of the FASTBUS specification. Both are implemented in ECL, and illustrate master and slave operation, arbitration circuit design, and logical and geographical addressing considerations.

Specifications for a fiv~channel differential transceiver for the FASTBUS Cable Segment have been developed.1*z The transceiver, CSX, is being planned as a full-custom integrated circuit implementation.Specification and development plans are discussed. The project is being carried out in collaboration with the NIM/FASTBUS Committee.