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Polycrystalline silicon thin-film transistors (TFTs) have been fabricated on glass substrates using a low temperature top-gate self-aligned process. The interface between the polysilicon active layer and the silicon dioxide oxide gate dielectric is of vital importance in order to achieve good thin-film transistor electrical characteristics. Carrier transport takes place within 10nm of this interface, and any roughness in this region, corresponding to the initial surface roughness of the polysilicon layer, causes scattering of the carriers and a higher density of interface traps. Chemical-mechanical polishing has been used to reduce the initial surface roughness of the polysilicon. Electrical parameters of polished TFTs, such as mobility and threshold voltage, show a marked improvement compared to unpolished devices.

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