No abstract

One of important parameter of Power MOSFET is ON resistance (RON) to minimize power loss in power system . To minimize RON, need high cell density process because channel resistance has occupied high proportional for total RON in low voltage Power MOSFET. Trench contact structure is suitable for high density device with narrow contact width. However in this structure case, designer should consider silicide formation due to high aspect ratio profile to prevent high leakage current. In this paper, present optimized Ti/TiN thickness formation to minimize leakage current between Drain and Source. Basically it shows good leakage performance that all removed Ti/TiN layer on the top of ILD by additional etchback or CMP process. And another finding from our study, optimized Ti/TiN formation also shows comparable leakage current with it. Unreacted Ti(+) ion is main contributed factor for high leakage current at P-channel device and higher wafer stress due to thicker TiN layer is another factor.