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In the paper, a novel implementation technique of orthogonal FIR systems is proposed. Starting from a state-space model of such a system, presented algorithm computes a fully pipeline structure consisting of Givens Rotations. This technique is illustrated by an FPGA hardware design example of a low-pass FIR filter.

This paper, presents a novel low power current mode 9 bit pipelined a/d converter. The a/d converter structure is composed of three 2.5 bit stages and one 3 bit stage operating in current mode and a final comparator which converts the analog current signal into a digital voltage signal. All the building blocks of the converter were designed in CMOS AMS 0.35 μm technology, simulated, and then a prototype converter was manufactured and measured to verify the proposed concept. The performances of the converter are compared to performances of known voltage-mode switched-capacitance and current-mode switched-current converter structures. Low power consumption and small chip area are the advantages of the proposed converter.

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In this paper novel AB class neuron structures that set foundations for low power VLSI neural networks and other applications are proposed. The analog AB class building blocks for sigmoidal characteristic neuron cells and programmable weight synaptic connections are presented and discussed. A qualitative comparison is made between standard and proposed neuron cells.