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An array cell ( A C ) architecture is described, which is dedicated to low-power design of N M O S 4-phase dynamic logic. This AC is constructed of ( M x N ) + 2 transistors so as to constitute each type of N M O S 4-phase logic gate. The structure regularity of the A C contributes m u c h toward the reduction of the total layout area. A number of experimental results demonstrate that not only the low-power dissipation but also the high density of a logic macro can be attained by the N M O S 4-phase dynamic logic.

Abstract| An array cell (AC) architecture for the layout design is described, which is dedicated to lowpower design by means of the NMOS 4-phase dynamic logic. An AC is constructed of (M2N)+2 transistors so as to constitute each t ype of NMOS 4-phase logic gates. A graph theoretic approach is exploited in the layout design to reduce the layout area. A n umber of experimental results demonstrate the practicability o f the proposed approach.