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Abstract-In this paper, the VLSI implementation of a realtime EZW video coder is presented. The proposed architecture adopts a modified 2-D DWT subband decomposition scheme, with the purpose of reducing the transposition memory requirements of 2-D DWT. In addition, through the use of a parallelized partial zerotree EZW scheme, temporary buffer requirements between the DWT and EZW modules are also reduced. The video encoder is integrated in a 0.35 um 3LM chip by using 341 K transistors on a 4.93×4.93 mm 2 die.

An array cell ( A C ) architecture is described, which is dedicated to low-power design of N M O S 4-phase dynamic logic. This AC is constructed of ( M x N ) + 2 transistors so as to constitute each type of N M O S 4-phase logic gate. The structure regularity of the A C contributes m u c h toward the reduction of the total layout area. A number of experimental results demonstrate that not only the low-power dissipation but also the high density of a logic macro can be attained by the N M O S 4-phase dynamic logic.

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