Parasitic capacitance modeling for multilevel interconnects

Tani, Shuntaro; Uchida, Yoshihiko; Furuie, Makoto; Tsukiyama, Shuji; Lee, BuYeol; Nishi, Shuji; Kubota, Yūsuke; Shirakawa, Isao; Imai, Shigeki

doi:10.1109/apccas.2002.1114908

Cited by 3 publications

(2 citation statements)

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“…These methods solve electromagnetic equations and usually provide accurate results. However, they are typically computationally expensive when applied in the modern very large-scale integration (VLSI) circuits [5]. Thus, they are normally deployed for the verification purpose before tapeout rather than being used as an estimator within loops of optimization.…”

Section: Prior Work and Literature Reviewmentioning

confidence: 99%

“…However, these equations often fail to work well for smaller geometries. Tani et al [5] also proposed approximation equations for parasitic capacitance extraction with promising results for some particular cases (e.g., two crossing metal lines). Their analytic method also includes several empirical factors that are hard to determine for new technologies.…”

Section: Prior Work and Literature Reviewmentioning

confidence: 99%

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New Analytic Model of Coupling and Substrate Capacitance in Nanometer Technologies

Shomalnasab

Zhang

2015

IEEE Trans. VLSI Syst.

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In this paper, we propose a new modeling method for computing coupling capacitance between interconnects on the same or different layers and substrate capacitance in the nanometer very large-scale integration circuits. The model has been developed based on a template, which is obtained on the basis of electric field approximation and followed by a curvefitting technique to reach promising accuracy. To verify our proposed model, we develop scripts to generate thousands of layout samples which cover all possible geometric situations for CMOS 180-, 90-, and 65-nm technologies. The proposed model is compared with previously published works with reference to the extracted results from commercial tools. The experimental results show that the estimation errors of our method are much lower than 10% (2%-4% or less for most of the cases) but with significantly reduced computation effort. The proposed model is a general methodology that can be used for any nanometer technologies with different geometric parameters.

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Section: Prior Work and Literature Reviewmentioning

confidence: 99%

Section: Prior Work and Literature Reviewmentioning

confidence: 99%