Analog FIR filtering is proposed to improve the performance of a single stage gm-C channel selection filter for ultra low power Internet-of-Things receivers. The transconductor is implemented as a Digital-to-Analog Converter; allowing a varying transconductance in time, which results in a very sharp FIR filter. The filter is manufactured in 22 nm FDSOI and has a core area of 0.09 mm 2. It consumes 92 µW from a 700 mV supply and achieves f −60dB /f −3dB = 3.8. The filter has 31.5 dB gain, out-of-band OIP3 of 28 dBm and output referred 1-dB compression point of 3.7 dBm. The filter bandwidth is tunable from 0.06 to 3.4 MHz.

No abstract

High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4GHz ISM-band. In addition, low power consumption is very important for IoT receivers. We propose a 2.4GHz zero-IF receiver front-end architecture that reduces power consumption by 2× compared to state-of-the-art and improves selectivity by >20dB without compromising on other receiver metrics. To achieve this the entire receive chain is optimized. The LNTA is optimized to combine low noise with low power consumption. Stateof-the-art sub-30nm CMOS processes have almost equal strength complementary FETs, which result in altered design trade-offs. A Windmill 25%-duty cycle frequency divider architecture is proposed that uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog FIR filter is implemented to provide very high receiver selectivity with ultra low power consumption. The receiver front-end is fabricated in a 22nm FDSOI technology and has an active area of 0.5mm 2 . It consumes 370µW from a 700mV supply voltage. This low power consumption is combined with 5.5dB noise figure. The receiver front-end has -7.5dBm IIP3 and 1-dB gain compression for a -22dBm blocker; both at maximum gain of 61dB. From three channels offset onward the adjacent channel rejection is ≥63dB for BLE, BT5.0 and IEEE802.15.4.

Analog FIR filtering is proposed to improve the performance of a single stage gm-C channel selection filter for ultra low power Internet-of-Things receivers. The transconductor is implemented as a Digital-to-Analog Converter; allowing a varying transconductance in time, which results in a very sharp FIR filter. The filter is manufactured in 22 nm FDSOI and has a core area of 0.09 mm 2 . It consumes 92 µW from a 700 mV supply and achieves f −60dB /f −3dB = 3.8. The filter has 31.5 dB gain, out-of-band OIP3 of 28 dBm and output referred 1-dB compression point of 3.7 dBm. The filter bandwidth is tunable from 0.06 to 3.4 MHz.