In this paper, we consider genetic algorithm to optimize the scan chain length of a given circuit and minimize the power dissipation during testing. For scan chain optimization, we use layout information so as to have a more accurate modeling of scan chain lengths. At the same time, we also try to minimize the test power by reducing switching activity in the scan flip-flops during scan test operation. The scan chain is partitioned into a specified number of sub chains in order to further minimize the scan chain length, routing overhead and test power. Experimental results have been reported on ISCAS-89 benchmark circuits.