Genetic Algorithm based Scan Chain Optimization and Test Power Reduction using Physical Information

Paul, Barun Bikash; Mukhopadhyay, Rajdeep; Gupta, Indranil

doi:10.1109/tencon.2006.344008

Cited by 10 publications

(1 citation statement)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Most of the work done on scan chains insertion and stitching ordering optimization assumes that placement information is available [9][10][11][12][13][14], meaning that it is actually reordering optimization. In all the cases, scan (re)ordering is reduced to the problem of the Traveling Salesman Problem in a suitable graph.…”

Section: Introductionmentioning

confidence: 99%

A Graph‐Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions

Zaourar

Kieffer

Aktouf³

2012

VLSI Design

View full text Add to dashboard Cite

The scan chain insertion problem is one of the mandatory logic insertion design tasks. The scanning of designs is a very efficient way of improving their testability. But it does impact size and performance, depending on the stitching ordering of the scan chain. In this paper, we propose a graph-based approach to a stitching algorithm for automatic and optimal scan chain insertion at the RTL. Our method is divided into two main steps. The first one builds graph models for inferring logical proximity information from the design, and then the second one uses classic approximation algorithms for the traveling salesman problem to determine the best scan-stitching ordering. We show how this algorithm allows the decrease of the cost of both scan analysis and implementation, by measuring total wirelength on placed and routed benchmark designs, both academic and industrial.

show abstract