Multi-core machines enable the possibility of parallel computing in Automatic Test Pattern Generation (ATPG). With sufficient computing power, previously proposed parallel ATPG has reached near linear speedup. However, test inflation in parallel ATPG yet arises as a critical problem and limits its practicality. Therefore, we developed a parallel ATPG system that incorporates (1) concurrent interruption (CI), (2) ripple compaction (RC) and (3) fan-in-cone based fault ordering (FIC) to deal with such problem. Concurrent interruption aborts test generation on simultaneously detected faults by fault simulation. Ripple compaction combines tests for different faults while fan-in-cone based fault ordering strategically arranges the fault list to reduce the number of test generations and thus speeds up the ATPG process. According to our experiments, the proposed parallel ATPG system effectively reduces 11% pattern count and achieves ∼0% test inflation while maintaining an average of 6.5X speedup with no attenuation in fault coverage on experimental circuits. I. . INTRODUCTIONAs VLSI designs continue to grow in size and complexity, the demand for faster ATPG arises for their verification testing. The conventional ATPG algorithm running on single processor has reached its bottleneck and become unsustainable to generate quality tests effectively for modern designs. The rapid development of multi-core processors enables the possibility of parallel computing and emerges to be a solution for scaled designs. By its communication protocol, a parallel computing architecture can be classified into: shared-memory system and message-passing system. Both parallel computing systems provide additional computing power and thus are used in [1] [2][10] to speed up ATPG recently.Common strategies used in parallel ATPG include fault parallelism, heuristic parallelism, search-space parallelism, algorithmic parallelism, and circuit parallelism. Fault parallelism [4] divides all faults among available processors and each processor generates tests for its corresponding faults. For heuristic parallelism [5], each processor employs a distinctive ATPG algorithm to generate a test for the same fault. Search-space parallelism [5] allows the processors to work collectively in finding a test for a single fault by dividing search space into discrete pieces and let each processor work on these search spaces simultaneously. ATPG algorithms are divided into fine- Fig. 1. Test-inflation problem in parallel ATPG grained tasks and processors work in parallel on each task in algorithmic parallelism [6]. For circuit parallelism [7], the circuit is divided into disjoint sub-circuits and each processor will perform ATPG operations on its respective part.Although various parallelism approaches were proposed, the core of parallel ATPG does not vary with these approaches and involves only two major operations: test generation and fault simulation. Krishnaswamy et al. in [8] parallelized fault simulation but overlooked test generation. Yeh et al. in [2] demonstrate...

No abstract

No abstract

No abstract

Timing analysis becomes profound for modern VLSI designs. Functional timing analysis (FTA) has emerged to eliminate false paths and provide better timing closure than traditional static timing analysis (STA). However, signal transitions effect, such as multiple input switching (MIS), which changes the pin-to-pin delay of a gate as well as the overall circuit delay, has not yet been considered in FTA. Therefore, a Transition-Aware FTA (TA-FTA) engine using a novel four-valued encoding for calculating true delay under the signal-transition effect is developed in this work. However, timing analysis becomes sophisticated once the signaltransition effect is concerned. Therefore, two techniques, cone separation and filtering (CSF) and quadratic dynamic search (QDS), are also proposed to speed up TA-FTA by more than two orders in time. Experimental results shows that after considering the MIS effect, in the benchmark circuits, the delay reported by our TA-FTA increases by 23% on average and by 38% for the worst case.