Suppressing test inflation in shared-memory parallel Automatic Test Pattern Generation

Abstract

Multi-core machines enable the possibility of parallel computing in Automatic Test Pattern Generation (ATPG). With sufficient computing power, previously proposed parallel ATPG has reached near linear speedup. However, test inflation in parallel ATPG yet arises as a critical problem and limits its practicality. Therefore, we developed a parallel ATPG system that incorporates (1) concurrent interruption (CI), (2) ripple compaction (RC) and (3) fan-in-cone based fault ordering (FIC) to deal with such problem. Concurrent interruption aborts test generation on simultaneously detected faults by fault simulation. Ripple compaction combines tests for different faults while fan-in-cone based fault ordering strategically arranges the fault list to reduce the number of test generations and thus speeds up the ATPG process. According to our experiments, the proposed parallel ATPG system effectively reduces 11% pattern count and achieves ∼0% test inflation while maintaining an average of 6.5X speedup with no attenuation in fault coverage on experimental circuits. I. . INTRODUCTIONAs VLSI designs continue to grow in size and complexity, the demand for faster ATPG arises for their verification testing. The conventional ATPG algorithm running on single processor has reached its bottleneck and become unsustainable to generate quality tests effectively for modern designs. The rapid development of multi-core processors enables the possibility of parallel computing and emerges to be a solution for scaled designs. By its communication protocol, a parallel computing architecture can be classified into: shared-memory system and message-passing system. Both parallel computing systems provide additional computing power and thus are used in [1] [2][10] to speed up ATPG recently.Common strategies used in parallel ATPG include fault parallelism, heuristic parallelism, search-space parallelism, algorithmic parallelism, and circuit parallelism. Fault parallelism [4] divides all faults among available processors and each processor generates tests for its corresponding faults. For heuristic parallelism [5], each processor employs a distinctive ATPG algorithm to generate a test for the same fault. Search-space parallelism [5] allows the processors to work collectively in finding a test for a single fault by dividing search space into discrete pieces and let each processor work on these search spaces simultaneously. ATPG algorithms are divided into fine- Fig. 1. Test-inflation problem in parallel ATPG grained tasks and processors work in parallel on each task in algorithmic parallelism [6]. For circuit parallelism [7], the circuit is divided into disjoint sub-circuits and each processor will perform ATPG operations on its respective part.Although various parallelism approaches were proposed, the core of parallel ATPG does not vary with these approaches and involves only two major operations: test generation and fault simulation. Krishnaswamy et al. in [8] parallelized fault simulation but overlooked test generation. Yeh et al. in [2] demonstrate...

Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems

“…The rest of this section compares the proposed methodology with the most relevant and recent parallel approaches considering the shared memory multi-core architecture model, such as [9]- [11], [13]. Where available, results are compared directly for the common benchmarks.…”

“…An 8-core system is considered in [9] and compared with an implementation of [13]. Fig.8 compares the speed-up of the proposed methodology with that of [9] and [13], as reported in [9].…”

“…This is achieved mainly due to the optimizations (discussed in Section III), which minimize redundant work by immediate updating of the fault status. Comparison regarding the test set size reduction is not possible with [9] as absolute values for test set sizes as well as corresponding fault coverage are not provided.…”

“…Similarly to the above approaches, the work proposed here is targeted towards achieving high degree of speed-up, as the number of available cores increases, and at the same time limiting test set inflation. A more elaborated comparison with the results of the works of [9]- [13] can be found in Subsection V-A.…”

“…Parallelization speed-up rates and test set inflation for shared memory architectural models are investigated in [9]- [13]. Shared memory is utilized in [9] as a low latency communication mean with high capacity to leverage synchronization and communication of the process with the goal of minimizing test inflation. Fault coverage is maintained while pattern count is reduced but at the expense of linearly scalable speed-up.…”