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In this paper, we show that the paradigm of Multiclock EsTEREL can be effectively used for the design of asynchronously communicating distributed systems. First we show that the protocol used in MulticlockEsTEREL for the modeling of VHDL can be used for the design of asynchronous interaction of processes, and an analysis can be made relative to speed or periodicity of the underlying processes for a safe implementation without missing any signals. The analysis also shows that one can arrive at a tradeoff between the periodicity and the buffer requirements on the average over a sequence of periods. Then, we illustrate the modeling of communicating reactive processes (which is essentially a network of EsTEREL nodes communicating via the rendezvous mechanism) as an instance of Multiclock EsTEREL.

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