Multiclock Esterel: a reactive framework for asynchronous design

Rajan, Basant; Shyamasundar, R. K.

doi:10.1109/ipdps.2000.845982

Cited by 13 publications

(10 citation statements)

References 7 publications

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“…Asynchronous circuits suffer from lack of mature design flow, and efforts are being made to capture the asynchronous behaviour of the GALS system in the synchronous domain. One effort in this direction is of multi-clock Esterel [4].…”

Section: Multi-clock Esterelmentioning

confidence: 99%

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Asynchronous on-chip networks

Amde¹,

Felicijan²,

Efthymiou³

et al. 2006

System-on-Chip: Next Generation Electronics

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Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs. They facilitate modular design and possess greater resilience to fabrication time inter-chip and run-time intra-chip process variability. They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g. on clock skew, by having asynchronous communication between modules. A few methodologies, including globally asynchronous, locally synchronous and desynchronisation, aim at leveraging the benefits of both synchronous and asynchronous design paradigms. The authors survey various methodologies used for leveraging asynchronous on-chip communication. They investigate various GALS based implementations, desynchronisation strategies and asynchronous network-on-chip (NoC) designs.

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Section: Multi-clock Esterelmentioning

confidence: 99%

“…In [4] the authors show an example design of a Micropipeline in a modular fashion and show that multi-clock Esterel modules could be composed in a hierarchical fashion.…”

Section: Multi-clock Esterelmentioning

confidence: 99%

Asynchronous on-chip networks

Amde¹,

Felicijan²,

Efthymiou³

et al. 2006

System-on-Chip: Next Generation Electronics

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“…We begin with a method for modeling the VHDL feature of scheduling events at later instants in Multiclock ESTEREL as proposed in [1,9]. The broad block diagram of the modeling is shown in Fig.…”

Section: Modeling Interaction Between Asynchronous Processesmentioning

confidence: 99%

“…Under this assumption, the underlying protocol for scheduling of events is depicted in Fig. 2 The steps of the implementation as proposed in [1,9] are given below:…”

Section: Modeling Interaction Between Asynchronous Processesmentioning

confidence: 99%

“…In a limited way, the concept of hierarchical network of synchronous nodes was introduced in Hierarchical CRP [12] without integrating the two notions of parallelism. In [1,9,10], the paradigm of Multiclock ESTEREL has been proposed as a unified framework for synchrony and asynchrony that overcomes the need to distinguish the various levels of concurrency. Some of the distinguishing features of Multiclock ESTEREL that set it apart from its predecessor ESTEREL are:…”

Section: Introductionmentioning

confidence: 99%

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Modeling Distributed Embedded Systems In Multiclock Esterel

Rajan¹,

Shyamasundar

2000

IFIP Advances in Information and Communication Technology

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In this paper, we show that the paradigm of Multiclock EsTEREL can be effectively used for the design of asynchronously communicating distributed systems. First we show that the protocol used in MulticlockEsTEREL for the modeling of VHDL can be used for the design of asynchronous interaction of processes, and an analysis can be made relative to speed or periodicity of the underlying processes for a safe implementation without missing any signals. The analysis also shows that one can arrive at a tradeoff between the periodicity and the buffer requirements on the average over a sequence of periods. Then, we illustrate the modeling of communicating reactive processes (which is essentially a network of EsTEREL nodes communicating via the rendezvous mechanism) as an instance of Multiclock EsTEREL.

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Compositional Reactive Semantics of SystemC and Verification with RuleBase

Shyamasundar

Doucet

Gupta

et al. 2007

Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems

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We present a behavioral semantics of SystemC that succinctly captures its reactive features, clock and time references, macro-and micro-time model, and allows the specification of a network of synchronous and asynchronous components communicating through either high-level transactions or low-level signal and event communications. The proposed semantic framework demonstrates the anomalies introduced by the simulation kernel, in spite of the macro-and micro-time scales. The framework further relates the simulation and logical correctness and provides a technique for scaling up the verification while keeping the correctness intact. Furthermore, we translate SystemC components to RuleBase using our semantic characterization that permits testing and verification of heterogenous designs. We illustrate the verification of a Central Locking System (CLS) designed in SystemC.

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Multiclock Esterel: a reactive framework for asynchronous design

Cited by 13 publications

References 7 publications

Asynchronous on-chip networks

Asynchronous on-chip networks

Modeling Distributed Embedded Systems In Multiclock Esterel

Compositional Reactive Semantics of SystemC and Verification with RuleBase

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