No abstract

Packaging of semiconductor chips, especially MEMSbased, always causes stress on the functional areas of the die causing unpredictable changes in chip performance. As a consequence such devices can only be calibrated individually after complete assembly. Melexis and TNO have developed an approach to reduce significantly packaging stress effects by means of additive manufacturing of the die package. The device is calibrated in a standard package with a standard calibration tool whereas the client specific shape is realized with additive manufacturing afterwards. The placement of a dedicated nozzle onto a SOIC16 package with a silicon pressure sensor illustrates the approach. Additive M anufacturingContinued advances in material properties and processing speed brought micro stereolithography (µ-SLA) into industrial manufacturing. For specific geometrical requirements and/or small series (down to 1 piece), µ-SLA has become a costeffective alternative to mold based processes. The micro stereolithography technology is elaborately described in numerous publications, as e.g. in refs [1] and [2]. BackgroundThe manufacturing of 3D objects by stereolithography is based on the spatially controlled solidification of a liquid resin by photo polymerization. Layer-by-layer the product is built, thus allowing for maximum freedom of form. To produce a layer a light projector is used to illuminate a pattern on the surface of a resin with a controlled illumination depth. As a result of this, the resin in the illuminated pattern is solidified and a product layer is formed. Both laser based light systems and Digital Light Processing (DLP) are methods to illuminate the resin. In DLP a digital micro mirror device (DMD) is used, which projects a complete 2-dimensional pixel-pattern, so a complete layer of resin can be cured at once. This method minimizes processing time and allows for smaller pixel sizes than laser based stereolithography.

The current trend in IC packaging towards an ever increasing degree of integration, combined with a high level of production flexibility calls for novel approaches in manufacturing. To address these challenges in a flexible manufacturing setting, TNO investigated to what extend mask-less additive manufacturing (3D printing) can be applied to packaging of semiconductor components and systems. The micro-stereolithography (μSLA) process has been applied to two different cases to assess its feasibility in creating integrated chip packages and interconnects. First, 2D interconnects based on conductive inks have been integrated into thin layers, manufactured using μSLA. In principle, this process allows building a 3D interconnect circuit on a layer-by-layer basis. A second approach is to build a fully functional, densely integrated system based on a 3D interconnect structure in μSLA resin (insulator) followed by global metallization and a trimming step. This approach allows creating almost free form interconnects integrated with functional properties in the package. These process examples allow manufacturing of small series with complex, integrated packages. Therefore, to asses the industrial relevance, the cost-of-ownership of manufacturing with the μSLA process on 200 mm wafers is estimated as a comparison to wafer-level molding. It will be shown that, especially in cases where complex geometries, integrated functionality or small series are required, mask-less additive manufacturing enables novel manufacturing solutions at reasonable cost.

A positioning system has been developed that places dies quickly and with high accuracy on a rigid substrate. The increased accuracy makes it possible to stack dies, or use dies with an ultra fine pitch, while not sacrificing speed. A single camera system determines the position of the die on the bondhead, as well as the position of the substrate. As a result, the effect of thermal drift is minimized. In order to decrease the cycle time, the camera system is mounted on the bondhead, so that the die position can be measured while moving. This concept has been successfully integrated and tested on an existing component mounter machine. The resulting accuracy has been increased from 10 to 3 μm (3σ), while the placement cycle time can be reduced by 20 %.