The numerous emerging implementations of RISC-V processors and frameworks underline the success of this Instruction Set Architecture (ISA) specification. The free and open source character of many implementations facilitates their adoption in academic and commercial projects. As yet it is not easy to say which implementation fits best for a system with given requirements such as processing performance or power consumption. With varying backgrounds and histories, the developed RISC-V processors are very different from each other. Comparisons are difficult, because results are reported for arbitrary technologies and configuration settings. Scaling factors are used to draw comparisons, but this gives only rough estimates. In order to give more substantiated results, this paper compares the most prominent open-source application-class RISC-V projects by running identical benchmarks on identical platforms with defined configuration settings. The Rocket, BOOM, CVA6, and SHAKTI C-Class implementations are evaluated for processing performance, area and resource utilization, power consumption as well as efficiency. Results are presented for the Xilinx Virtex UltraScale+ family and GlobalFoundries 22FDX ASIC technology. CCS CONCEPTS• Computer systems organization → System on a chip; Serial architectures.

Microcontrollers require protection against transient and permanent faults when being utilized for safetycritical and highly reliable applications. Fail safe Dual Core Lockstep architectures are widely used in the automotive domain; the aerospace domain utilizes fail functional TMR or higher redundancy. This work incorporates fault tolerance techniques of those domains into a framework for RISC-V processors. The implemented fault tolerance components are highly configurable to satisfy various dependability requirements. The cost of applied fault tolerance mechanisms is evaluated for both an FPGA and an ASIC implementation. Fault injection tests prove the effectiveness for error detection and cover both transient and permanent faults in logic and memories. New methods are introduced to minimize the error detection latency and achieve a reduction of up to 79%.