A low-power interferer-robust mixer-first receiver front-end that uses a novel capacitive stacking technique in a bottom-plate N-path filter/mixer is proposed. Capacitive stacking is achieved by reading out the voltage from the bottom-plate of N-path capacitors instead of their top-plate, which provides a 2x voltage gain after down-conversion. A step-up transformer is used to improve the out-of-band (OOB) linearity performance of small switches in the N-path mixer, thereby reducing the power consumption of switch drivers. This paper explains the concept of implicit capacitive stacking and analyzes its transfer characteristics. A prototype chip, fabricated in 22 nm FDSOI technology, achieves a voltage gain of 13 dB and OOB IIP3/IIP2 of +25/+66 dBm with 5 dB Noise figure while consuming only 600 µW of power at fLO=1 GHz. Thanks to the transformer, the prototype can operate in the input frequency range of 0.6-1.2 GHz with more than 10 dB voltage gain and 5-9 dB Noise figure. Thus it opens up the possibility of low-power software defined radios.

This paper presents a sub-mW mixer-first RF front-end that exploits a novel capacitive stacking technique in an altered bottom-plate N-path filter/mixer to achieve passive voltage gain and high-linearity at low noise figure. Capacitive stacking is realized implicitly by reading out the voltage from the bottom-plate of N-path capacitors instead of their top-plate, which provides a 2x gain at the read-out capacitors. Additional passive voltage gain is achieved using impedance upconversion while improving the out-of-band linearity performance of small switches. With no other active circuitry, only clock generation circuits determine the total power consumption of this RF frontend. A prototype is fabricated in GF22 nm FDSOI technology. Operating at fLO= 1 GHz, the prototype achieves a voltage gain of 13 dB, 5 dB Noise Figure and +25/+66 dBm Out-of-band IIP3/IIP2 at 160 MHz offset while consuming only 600 µW of power from a 0.8 V supply.