We report a significant reduction in the lattice thermal conductivity of the CoSb3 skuttertudites, doped with chalcogen atoms. Te/Se chalcogen atoms doped CoSb3 skutterudite samples (Te0.1Co4Sb12, Se0.1Co4Sb12, Te0.05Se0.05Co4Sb12) are processed by ball milling and spark plasma sintering. X-ray diffraction data combined with energy dispersive X-ray spectra indicate the doping of Te/Se chalcogen atoms in the skutterudite. The temperature dependent X-ray diffraction confirms the stability of the Te/Se doped CoSb3 skutterudite phase and absence of any secondary phase in the temperature range starting from 300 K to 773 K. The Raman spectroscopy reveals that different chalcogen dopant atoms cause different resonant optical vibrational modes between the dopant atom and the host CoSb3 skutterudite lattice. These optical vibrational modes do scatter heat carrying acoustic phonons in a different spectral range. It was found that among the Te/Se chalcogen atoms, Te atoms alter the host CoSb3 skutterudite lattice vibrations to a larger extent than Se atoms, and can potentially scatter more Sb related acoustic phonons. The Debye model of lattice thermal conductivity confirms that the resonant phonon scattering has important contributions to the reduction of lattice thermal conductivity in CoSb3 skutterudites doped with Te/Se chalcogen atoms. Lattice thermal conductivity ∼ 0.9 W/mK at 773 K is achieved in Te0.1Co4Sb12 skutterudites, which is the lowest value reported so far in CoSb3 skutterudites, doped with single Te chalcogen atom.

No abstract

This work presents a voltage mode scheme of a full-wave precision rectifier circuit using an analog building block differential voltage current conveyor transconductance amplifier (DVCCTA) including five NMOS transistors. The proposed design is essentially suited for low voltage and high-frequency input signals. The operation of the proposed rectifier design depends upon the region of operation of NMOS transistors. The output waveform of the presented rectifier design can be made electronically tunable by controlling the bias voltage. The functional correctness and verification of the presented design are performed using 0.25-µm TSMC technology under the supply voltage of ±1.5 V. The absence of a resistor leads to a minimal parasitic effect. To obtain further insight on the robustness of the circuit, a Monte Carlo simulation and corner analysis are also presented. The circuit is verified experimentally by incorporating a breadboard model with the help of commercially available ICs CA3080 (operational transconductance amplifier) and AD844AN (current feedback operational amplifier) and offers remarkable compliance with both theoretical and simulation outcomes. The presented design has been laid out on Cadence virtuoso, which consumes a chip area of 9044 µm2.

No abstract

No abstract