State-of-the-art hypergraph partitioners follow the multilevel paradigm that constructs multiple levels of progressively coarser hypergraphs that are used to drive cutsize refinement on each level of the hierarchy. Multilevel partitioners are subject to two limitations: (i) hypergraph coarsening processes rely on local neighborhood structure without fully considering the global structure of the hypergraph; and (ii) refinement heuristics risk entrapment in local minima. In this paper, we describe K-SpecPart, the first supervised spectral framework that directly tackles these two limitations. K-SpecPart solves a generalized eigenvalue problem that captures the balanced partitioning objective and global hypergraph structure in a low-dimensional vertex embedding while leveraging initial high-quality solutions from multilevel partitioners as hints. Specifically, in the context of multi-way partitioning, K-SpecPart derives multiple bipartitioning solutions from a multi-way hint partitioning solution. These bipartitioning solutions are independently integrated into the generalized eigenvalue problem to compute several eigenvectors, inducing a large-dimensional embedding. We apply Linear Discriminant Analysis (LDA) to transform this large-dimensional embedding into a lower-dimensional embedding. K-SpecPart further constructs a family of trees from the vertex embedding and partitions them with a tree-sweeping algorithm. We extend the tree partitioning algorithm of SpecPart [30] to handle multiway partitioning. The multiple tree-based partitioning solutions are overlaid, followed by lifting to a clustered hypergraph, where an ILP (integer linear programming) partitioning problem instance is solved. Our empirical studies substantiate the benefits of K-SpecPart. For bipartitioning, K-SpecPart produces superior solutions to SpecPart with improvements in some cases of up to ∼30%. For multi-way partitioning, K-SpecPart produces superior solutions to hMETIS and KaHyPar with improvements in some cases of up to ∼20%.

Objective of this paper is to enhance the throughput of Blowfish block cipher by designing a pipelined architecture of the same followed by implementation and evaluation of its performance in Field Programmable Gate Array. The proposed architecture was implemented by using Verilog HDL and was synthesized, placed and routed in Spartan3E chip XC3s500e-5fg320 using ISE Design Suite 12.1. Performance analysis of the proposed pipelined design shows a throughput of 6.3 Gbps as compared to 588.255 Mbps for non-pipelined design.