The effect of adjacent bit-line (BL) cell interference on BL current fluctuation (ΔI BL = high I BL − low I BL ) due to random telegraph noise (RTN) in floating-gate NAND Flash cell strings is characterized. It was found that the electron current density (J e ) of a read cell can be appreciably different depending on the position in the channel width direction because of the interference from adjacent BL cells. The interference can be controlled by the state (program or erase) of the adjacent cells. We verified that ΔI BL due to RTN increases as a high-J e position is controlled to be close to a trap position in 32-nm NAND Flash memory strings. Finally, it was also shown that the adjacent cell interference affects not only ΔI BL but also the ratio of capture and emission time constants [ln(τ c /τ e )].Index Terms-Bit-line (BL) current fluctuation, BL interference, capture and emission, floating gate, NAND Flash memory, random telegraph noise (RTN).

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The effect of adjacent bit-line (BL) interference on low frequency in 26 nm NAND flash memory was characterized. With the program (P) and erase (E) states of adjacent cells, current fluctuation (deltaI(BL)) and corner frequency (f(c)) of Lorentzian spectrum were changed. DeltaI(BL) due to RTN ranges from approximately 67.3 nA to approximately 45.9 nA with 4 different modes (P/P, P/E, E/P, E/E) of the state of adjacent cells and f(c) ranges from 48 Hz to 89 Hz. Using measured deltaI(BL) and extracted capture (tau(c)) and emission times (tau(e)) with 4 different modes, we calculated tau and f(c), and extracted the position of a trap in the channel width direction with deltaI(BL) and simulated data. The calculated data showed excellent agreement with measured spectra. Finally, we prepared energy band diagrams in P/P and P/E modes using 3-D device simulation and clarified the effect of adjacent bit-line cell interference. The control gate bias is slightly higher in P/P mode than P/E mode, and then trap energy in P/P mode is relatively lower than that in P/E mode, resulting in shorter capture time in P/P mode.

We characterized normalized noise power density (S I/I BL 2) and bit-line (BL) current fluctuation (ΔI BL) using traps generated applying cycling stress in 26 nm NAND flash memory. The ΔI BL, S I/I BL 2, and capture (τc) and emission times (τe) of random telegraph noise (RTN) were measured before and after cycling stress, respectively. With cycling stress, traps were generated, and S I/I BL 2 and ΔI BL were increased significantly. The τc and τe of RTN after cycling stress are similar with to those before cycling stress. RTN was characterized in terms of the trap position in the three-dimensional space (x T, y T, and z T) of the tunneling oxide and trap energy (E T). three-dimensional technology computer-aided design (TCAD) simulation was used to determine the position of z T through the effect of adjacent BL cells.