Results of complete 3-dimensional ac/dc characterizations of the npn transistor in a submicron BiCMOS technology are presented. Accuracy and throughput acceptable for constructing compact models is achieved through the use of multidimensional process simulation, adaptive grid generation and preconditioned iterative techniques for both dc and small-signal analysis. Comparisons of 2-and 3-dimensional simulations with measurements enable assessments of the magnitude of 3-dimensional effects, thereby suggesting efficient device optimization strategies.

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