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The objective of this work was to study the trench and contact hole shrink mechanism in negative tone develop resist processes and its manufacturability challenges associated for 20nm technology nodes and beyond. Process delay from post-exposure to develop, or "queue time", is studied in detail. The impact of time link delay on resolved critical dimension (CD) is fully characterized for patterned resist and etched geometries as a function of various process changes.In this study, we assembled a detailed, theoretical model and performed experimental work to correlated time link delay to acid diffusion within the resist polymer matrix. Acid diffusion is determined using both a modulation transfer function for diffusion and simple approximation based on Fick's law of diffusion.

Advanced thermal annealing processes used for transistor enhancing for the state of the art process nodes induce wafer grid deformations. RTA (Rapid Thermal Anneal) and LSA (Laser Scanning Anneal) processes are a few examples. High Order Wafer Alignment (HOWA) method is an effective wafer alignment strategy for wafers with distorted grid signature especially when wafer-to-wafer grid distortion variations are also present. However, usage of HOWA in high volume production environment requires 1) careful initial determination of optimum polynomial order and alignment sampling to be implemented, and 2) matched tool monitoring and controlling strategies and infrastructures to avoid potential HOWA induced drawbacks (i.e. alignment walking).

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