We report on a 65nm Ge pFET with a record performance of I on = 478µA/µm and I off,s = 37nA/µm @V dd = -1V. These improvements are quantified and understood with respect to halo/extension implants, minimizing series resistance and gate stack engineering. A better control of Ge in-diffusion using a low-temperature Epi-silicon passivation process allows achieving 1nm EOT Ge-pFET with increased performance. IntroductionRecently, 100nm Ge devices have shown similar intrinsic velocities and higher mobility compared to pMOS Si- (100) [1]. The high mobility/velocity at low V DS suggest Ge devices is an attractive option for future high performance MOS technologies. However, no results are available for GepMOSFET coupling low EOT and sub-70nm gate length. In this work, we demonstrate high performance p-channel Ge transistors with these two essential features.

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