The ESD failure mechanism of the EPI wafer device is reinvestigated, which is caused by the low substrate resistance induced transient current crowding. We also demonstrate that putting the ESD device in the deep-NWell (DNW) can effectively eliminate the low substrate resistance effect because the device in the DNW can be isolated from the P+ substrate. The DNW can not only improve the HBM and MM threshold voltages for EPI wafer device but also improve the CDM threshold voltage for EPI wafer and bulk wafer devices. Keywords-component; Human-body Model (HBM), Machine Model (MM), Charged-device model (CDM) style;

A novel failure mechanism of the high-voltage (HV) product during the negative-current-triggered (NCT) latch-up test is found. From the failure analysis and simulation results, the failure is identified as the unexpected parasitic-bipolar transistors turn-on induced the regulator malfunction to result in the low-voltage (LV) component damage. Latch-Up;Parasitic Bipolar; Circuit Impact ; ESDI.

This paper will describe a high performance 1 Mbit CMOS MASK ROM with access time as fast as 29 nsec. The fast accessing is achieved through bit line capacitance reduction, sensitive amplifier design, and double metal interconnection. Delta-I noise and ESD susceptibility problem have been cared.