The failure mechanism re-investigation Of ESD device on EPI wafer

Lee, Jian-Hsing; Kung, C.; Kung, E.; Shih, J.R.

doi:10.1109/irps.2012.6241892

Cited by 8 publications

(2 citation statements)

References 10 publications

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“…For a short‐duration pulse, the peak current of I ox can be approximated by [8]

I_{ox, peak} ≃ V_{normalCDM} / R

It is apparent that the oxide stress current I OX of the HVN1 transistor under the CDM test decreases inversely with the R PW from (2). However, the R PW varies with the body layout.…”

Section: Failure Mechanismmentioning

confidence: 99%

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Failure mechanism for input buffer under CDM test

et al. 2014

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The influence of the body layout on the charged device model (CDM) failure site and the robustness of the input buffer is explored. The failure analysis results confirm that the gate oxide is damaged. The failure site can be moved from the region above the channel to the overlap region between the source and the gate once the body layout is cut from a ring into a small segment, providing direct evidence demonstrating that the CDM current flows through the gate oxide via the body and the source of the transistor, since both connect to the Vss bus line. Otherwise, changing the body layout of the input buffer transistor does not vary the failure location.

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“…For a short‐duration pulse, the peak current of I ox can be approximated by [8]

I_{ox, peak} ≃ V_{normalCDM} / R

It is apparent that the oxide stress current I OX of the HVN1 transistor under the CDM test decreases inversely with the R PW from (2). However, the R PW varies with the body layout.…”

Section: Failure Mechanismmentioning

confidence: 99%

“…where Fig. 4 Cross-section and equivalent circuit for HVN1 transistor during CDM test For a short-duration pulse, the peak current of I ox can be approximated by [8]…”

mentioning

confidence: 99%