Application of the chemical mechanical polishing of silicon dioxide used as the interlevel dielectric in the manufacture of VLSI chips has led to the development of a relatively simple process for fabrication of the device wiring on such chips. The polishing process is used to remove the interlevel dielectric from the tops of interconnect studs and produce a planarized surface ready for the next level of wiring. The characteristics of this polishing process were studied on both blanket films of oxide and on wafers with device topography. Empirical relationships were found, and the results applied to device manufacture, resulting in process simplification while increasing chip reliability and yield.

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Re-emission coefficients for SiO2 films and for Si films deposited through rf sputtering have been measured as a function of pressure and input power. Values for SiO2 were 0.86−0.30 and for Si 0.45−0.07. High re-emission coefficients correlated with negative potentials on the deposit surface, which, in turn, caused resputtering of the deposit by positive ions drawn from the glow discharge. The existence of additional mechanisms for re-emission was established for rf-sputtered silicon deposited at zero substrate bias. The re-emission coefficient of dc-sputtered silicon was found to have values comparable to those of rf sputtering.

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