Vedic Mathematics, an ancient Indian technique can be used to solve any arithmetic problems in an easy and simple way. A novel high speed Vedic squaring and multiplier unit is designed using the principles of Yavadunam sutra and the bit reduction technique is projected in this paper. The complexity of the multiplier is reduced as the bit reduction technique is employed and later the Yavadunam sutra is implemented for the calculation of the deficiency. The size of the proposed N bit multiplier is reduced to N-1 bit and also considerable speed improvement is achieved. The architecture is designed and realized using Xilinx Spartan FPGA and synthesized using 90nm and 180nm technology synopsys device.

In current day situation we come across numerous mathematical challenges. This could be overwhelmed by the Vedic Mathematics. Vedic Mathematics is an ancient approach to solve problems in a rapid manner. In this paper the design of a novel Vedic square and multiplier architecture based on Yavadunam Sutra is proposed. Yavadunam is a squaring sutra of the Vedic Mathematics. We have designed a generic architecture for this squaring sutra and have designed a high speed Vedic binary multiplier architecture using the principles of Yavadunam sutra. The proposed multiplier offers significant improvement in speed. Xilinx Spartan FPGA is used to design and realize the architecture and the Synopsys device with 90 nm and 180 nm technology is used to synthesize the same.

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