VLSI Design of a Squaring Architecture based on Yavadunam Sutra of Vedic Mathematics

Deepa, A.; Marimuthu, C. N.

doi:10.1109/icesc48915.2020.9155768

Cited by 6 publications

(3 citation statements)

References 2 publications

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“…Every digital circuit has inherent delays, which might change as a result of manufacturing variation. The suggested PUF Extractor's simplified design is based on the route delay in traditional digital circuits [12][13][14].…”

Section: International Journal On Recent and Innovation Trends In Com...mentioning

confidence: 99%

A Novel Approach for Integrated Shortest Path Finding Algorithm (ISPSA) Using Mesh Topologies and Networks-on-Chip (NOC)

Karthick

Shankar²,

Jayakumar³

et al. 2023

IJRITCC

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A novel data dispatching or communication technique based on circulating networks of any network IP is suggested for multi data transmission in multiprocessor systems using Networks-On-Chip (NoC). In wireless communication network management have some negatives have heavy data losses and traffic of data sending data while packet scheduling and low performance in the varied network due to workloads. To overcome the drawbacks, in this method proposed system is Integrated Shortest Path Search Algorithm (ISPSA) using mesh topologies. The message is sent to IP (Internet Protocol) in the network until the specified bus accepts it. Integrated Shortest Path Search Algorithm for communication between two nodes is possible at any one moment. On-chip wireless communications operating at specific frequencies are the most capable option for overcoming metal interconnects multi-hop delay and excessive power consumption in Network-on-Chip (NoC) devices. Each node can be indicated by a pair of coordinates (level, position), where the level is the tree's vertical level and the view point is its horizontal arrangement in the sequence of left to right. The output gateway node's n nodes are linked to two nodes in the following level, with all resource nodes located at the bottommost vertical level and the constraint of this topology is its narrow bisection area. The software Xilinx 14.5 tool by using that overall performance analysis of mesh topology, each method are reduced data losses with better accuracy although the productivity of the delay is decreased by 21 % was evaluated and calculated..

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Section: International Journal On Recent and Innovation Trends In Com...mentioning

confidence: 99%

A Novel Approach for Integrated Shortest Path Finding Algorithm (ISPSA) Using Mesh Topologies and Networks-on-Chip (NOC)

Karthick

Shankar²,

Jayakumar³

et al. 2023

IJRITCC

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“…A collection of the ancient Indian mathematical tools and techniques called Vedic Mathematics , comprises of 16 Sutras (Formulae) [9]. "Urdhva-tiryakbyham" is a Sanskrit word which means "vertical and crosswise" formula, which is used as general case of multiplication [10]. "Nikhilam Navatascaramam Dasatah" also a Sanskrit term indicating "all from 9 and last from 10", formula is used for large number multiplication which are near to the base (i.e.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of FPGA Based Complex Floating Point Multiplier using CIFM

et al. 2023

IJFMR

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: Floating point multiplication is one of the crucial operations in many application domains such as image processing, signal processing etc. But every application requires different working features. Some need high precision, some need low power consumption, low latency etc. The multiplication process requires more hardware resources and processing time when compared with addition and subtraction. This paper presents, Design and Implementation of FPGA based Complex Floating Point Multiplier using Combined Integer and Floating point Multiplier (CIFM). The Processing speed of the multipliers decides the execution time of the system as it consumes most of the time. The design is implemented in VHDL and design is synthesized on FPGA to know the performance. The architectures for the three multiplier solutions of complex multiplier for 32 x 32 bit complex numbers multiplication are coded in VHDL and implemented through Xilinx ISE 13.4 navigator and Modelsim 5.6 and their performance is compared. The complex floating point multiplication with single precision using CIFM multiplier has comparatively less amount of delay and power consumption with respect to Vedic and Array multiplier.

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“…In 2020, Shamim Akhter et al [7], have used a different approach to implement base-2 squaring units by employing an improved VM to enhance the computation speed and reduce the design area. Whereas the authors in [19] have presented efficient squarer to be used for high-speed digital applications. This squarer's architecture is based on utilizing the Yavadunam algorithm that states of squaring a number are equivalent to the addition of the product of the number to be squared by the difference deficiency and the squaring of deficiency.…”

Section: Introductionmentioning

confidence: 99%

Vedic-Based Squarers with High Performance

Al-Assfor

AL-Furati

Rashed

2021

IJEEI

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Squaring operation represents a vital operation in various applications involving image processing, rectangular to polar coordinate conversion, and many other applications. For its importance, a novel design for a 6-bit squarer basing on the Vedic multiplier (VM) is offered in this work. The squarer design utilizes dedicated 3-bit squarer modules, a (3*3) VM, and an improved Brent-Kung Carry-Select Adder (IBK-CSLA) with the amended design of XOR gate to perform fast partial-products addition. The 6-bit squarer circuit can readily be expanded for larger sizes such as 12-bit and 24-bit numbers which are useful for squaring the mantissa part of 32-bit floating-point numbers. The paper also offers three architectures for 24-bit squarer using pipelining concept used in various stages. All these squaring circuits are designed in VHDL and implemented by Xilinx ISE13.2 and FPGA. The synthesis results reveal that the offered 6-bit, 12-bit, and 24-bit squarer circuits introduce eminent outcomes in terms of delay and area when utilizing IBK-CSLA with amended XOR gate. Also, it is found that the three architectures of 24-bit squarer present dissimilar delay and area, and the architecture design based on 3-bit squarer modules with (3*3) VM introduces the lowest area and delay.

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VLSI Design of a Squaring Architecture based on Yavadunam Sutra of Vedic Mathematics

Cited by 6 publications

References 2 publications

A Novel Approach for Integrated Shortest Path Finding Algorithm (ISPSA) Using Mesh Topologies and Networks-on-Chip (NOC)

A Novel Approach for Integrated Shortest Path Finding Algorithm (ISPSA) Using Mesh Topologies and Networks-on-Chip (NOC)

Design and Implementation of FPGA Based Complex Floating Point Multiplier using CIFM

Vedic-Based Squarers with High Performance

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