In high-power-density power electronics applications, it is important to predict the power losses of semiconductor devices in order to maximize global system efficiency and avoid thermal damages of the components. When different effects influence the power losses, some of which difficult to be physically modeled, it is worthwhile to use empirical laws obtained starting from experimental data, like the Steinmetz's equation widely used for inductors' magnetic core losses prediction. This paper discusses a method to find empirical power loss models by using Genetic Programming (GP). In particular, the GP approach has been applied to identify power losses in Insulated Gate Bipolar Transistors for Induction Cooking application. A loss model has been obtained using an experimental training set, and the result has been successively validated

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In this paper, we describe an inline method to reveal crystal defects in the device fabrication process by voltage contrast detection with an electron beam inspection tool. Suitably designed monitor structures are used to this purpose. The correspondence between bright voltage contrast defects and dislocations connecting the transistor source and drain is demonstrated by selective etching followed by SEM review and by TEM inspection. In addition, it is shown that the voltage contrast defects correlate with the leakage current of the dislocation monitor structures, though some electrically active defects are missed by the electron beam inspection. Possible approaches to improve the capture rate of dislocations and correlation to leakage current are discussed. Finally, the correlation between e beam inspection of dislocation monitor structures and parametric test on a 65nm DR wafer is demonstrated.