This paper presents a new generalized row-based global router suitable for standard cell, gate-array, and seaofgates integrated circuits. It is the jrst row-based global router to explicitly minimize chip area. This global router uses adaptive Steiner trees to minimize chip area. The results were vastly improved over typical minimum wire length Steiner trees. This global router automatically adapts to technologies. In addition, optimal feedthrough placement is accomplished using linear assignment. Throughout the algorithm, timing constraints are taken into account. Also, a unique vertical constraint cycle minimization step eases the task for LEA channel routers. Finally, it is shown that this global router outperformsother global routers for all of the MCNC benchmark circuits which were tested.